The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory control circuit for controling the activation period of an internal transfer operation of a refreshtype semiconductor memory using a memory cell in which stored data must be refreshed.
A dynamic random-access memory (to be hereinafter referred to as a DRAM) and a pseudo static RAM (to be hereinafter referred to as a PSRAM) are known as conventional refresh-type semiconductor memories. These memories include memory cells each comprising one MOS transistor and one capacitor. The word line of such a conventional refresh memory is driven as shown in FIG. 1. While chip enable signal CE is at low level "L" (active low), word line WL is kept open (active high). In this case, if signal CE is set at low level for a long period of time, the active pull-up level of the word line is reduced, by a leakage current, to below active level V.sub.H, and an "H" level having a sufficient potential cannot be written in the memory cell. Therefore, conventionally, a maximum value is assigned to time tCE, during which signal CE is at low level, thereby to limit the time period.
However, the refresh-type memory adapting the above word drive method is faced with the problem as to how it is to be connected to a CPU (Central Processing Unit) or an MPU (Microprocessing Unit) when it s used in a computer system. This situation will be described with reference to a timing chart of FIG. 2, in which a read operation of the CPU is illustrated.
In FIG. 2, reference symbol CLK denotes a system clock; AD, an address bus signal and data bus signal in the CPU; ALE, an address latch signal; and RD, a read signal. If an effective address signal is present in the address bus during a period of clock cycle T1, the CPU generates the ALE pulse.
On the other hand, in a refresh-type memory in which the maximum limit value (tCE max) exists in time tCE of signal CE as described before, a pulse of negative polarity, which completes in one read cycle, must be input to a CE terminal. Otherwise, a problem of level down in word line WL is posed.
Therefore, conventionally, signal ALE of FIG. 2 is not connected directly to the CE terminal at an interface between the CPU and the refresh-type memory. Rather, signal RD, which goes to low level during a period of clock cycle T2 and then goes to high level during a period of clock cycle T4, is supplied as signal CE to the CE terminal.
During a period of clock cycle T3, the CPU receives data of signal AD supplied, via the data bus, from the refresh-type memory. At this time, confirmation of the valid data is sometimes not yet completed. Therefore, an extra period of time, i.e., a wait cycle, must be undesirably included in the CPU overall operation time.
In order to eliminate the above problem, level down of the word line of the refresh-type memory, caused by the leakage current, may be prevented by, for example, a pump circuit. However, according to this method, (1) current consumption is increased by the addition of the pump circuit, and (2) self refreshing cannot be performed if the word line is kept open during a low-level period of signal CE.
To avoid the above problems, the applicant of the present invention has proposed a "Control Circuit for Semiconductor Memory Device" in Japanese Patent Application No. 61-30139. This application corresponds to U.S. patent application Ser. No. 012,315 filed on Feb. 9, 1987, (All disclosures of this U.S. application are incorporated in the present application.)
As is shown in the timing chart of FIG. 3, the control circuit of the above U.S. application is characterized by word line NWL being intermittently driven in the read mode and being continuously activated in the write mode in accordance with a write timing. When the word line is closed, the control circuit immediately precharges a bit line, etc., to start a refresh operation, and opens refresh word line RWL. However, according to this method, the word line must be driven differently in the read and write modes. As a result, the arrangement of the control circuit for driving the word line becomes undesirably complicated.